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宽带DRFM干扰机信号处理模块设计 被引量:2

Design of signal processors for broadband DRFM jammers
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摘要 目的:提高数字射频存储器(DRFM)干扰机的瞬时带宽、处理能力和灵活性等性能。方法:结合DRFM原理与信道化接收技术,提出了高性能宽带DRFM干扰机信号处理模块的设计方案,并据此采用先进的信号处理器件和高性能ADC、DAC设计硬件平台,完成相应的软件设计。结果:对硬件平台的性能参数进行测试,实验表明其瞬时带宽可达4 GHz,信号最大存储深度约为200 ms,最小转发延迟约为600 ns。结论:该原型机可实现对新体制雷达的有效干扰。 Aims: This paper aims to improve the instantaneous bandwidth, computing capability and flexibility of the digital radio frequency memory(DRFM) jammer. Methods: The DRFM principle and channelized receiving technology were combined to propose a design scheme of the signal processing module for high-performance broadband DRFM jammers. Meanwhile, advanced signal processing devices, high-performance ADCs and DACs were used to design a hardware platforms, with the corresponding software designed. Results: The experiment results showed that the instantaneous bandwidth of the hardware platform could reach 4 GHz, that the signal storage depth could reach round 200 ms, and that the minimum processing delay could reach round 600 ns. Conclusions: This prototype can achieve effective jamming to the new radar systems.
作者 侯晓宇 全大英 渐欢 金小萍 HOU Xiaoyu;QUAN Daying;JIAN Huan;JIN Xiaoping(Key Laboratory of Electromagnetic Wave Information Technology and Metrology of Zhejiang Province,College of Information Engineering,China Jiliang University,Hangzhou 310018,China)
出处 《中国计量大学学报》 2020年第2期272-278,共7页 Journal of China University of Metrology
基金 浙江省自然科学基金项目(No.LY17F010012)
关键词 数字射频存储 信道化技术 间歇采样转发干扰 JESD204B DRFM channelized technology interrupted sampling jamming JESD204B
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