摘要
近年来在人工智能领域,卷积神经网络(CNN)因为其优异的算法性能获得广泛应用。由于CNN的模型结构及卷积运算具有高度并行性,FPGA加速CNN成为硬件加速CNN的重要解决方案。本文针对典型的卷积神经网络LeNet-5,提出一种采用卷积-池化-卷积-池化-卷积五级层间流水线架构的卷积核间全并行、核内部分并行,输出部分并行加速方案,实现卷积神经网络卷积池化运算的硬件加速。实验结果表明,在129.8Mhz时钟频率及16bit定点精度的情况下,系统对单张图片的处理速度较CPU提高近337倍,能效比为13.68GOP/(s*W)。
In recent years,convolutional neural network(CNN)is widely used in field of artificial intelligence thanks to excellent algorithm performance.Due to high parallelism of the CNN model structure and the convolution operation,FPGA has been a promising hardware solution to accelerating the CNN.For the typical CNN network LeNet-5,in this paper an acceleration scheme adopting a convolutional-pooling-convolutional-pooling-convolutional five-level interlayer pipeline architecture is proposed,where hardware acceleration of CNN convolution pooling operation is realized with full parallelism between convolution kernels and partial parallelism within convolution kernel and at the output.Experiment results show that speed of system processing a single image increases by about 337 times compared with that of the CPU in the case of 129.8Mhz clock frequency and 16bits fixed-point precision,achieving energy efficiency ratio of 13.68GOP/(s*W).
作者
李莉
陈心宇
高文斌
LI Li;CHEN Xinyu;GAO Wenbin(Beijing Electronic Science and Technology Institution,Beijing 100070,P.R.China)
出处
《北京电子科技学院学报》
2022年第4期96-104,共9页
Journal of Beijing Electronic Science And Technology Institute
基金
北京高校“高精尖”学科建设项目(项目编号:20210069Z0402)
2020教育部一流本科专业建设项目(项目编号:gjylzy2021001)
国家重点研发计划基金资助项目(项目编号:2017YFB0801803)
关键词
卷积神经网络
FPGA
硬件加速
流水线架构
convolutional neural network(CNN)
FPGA
hardware acceleration
pipeline architecture
