摘要
文章介绍了一种单精度浮点RISC微处理器的核心设计思想,改进设计了一种新颖的芯片内置总线仲裁器控制总线、中断处理机管理中断、数据中继器操作存储器。采用三阶布斯算法和浮点并行算法设计FALU和FMUL,并设计了嵌入式128KSRAM,最后用UMC0.25滋mCMOS工艺库进行综合、布局布线完成版图设计。版图后模拟验证以及CPLD硬件仿真验证表明:微处理器工作主频达到50MHz,全部共88条指令运行正常。
This paper describes the design of a 43-bit floating-point RISC microprocessor with double precision. Several innovations, which include a new type of embedded bus arbiter control bus, a new type of trap handler manage interrupt, a new type of data link control memory and the high order Booth's algorithm, are used to design this microprocessor. 128K SRAM is also embedded in microprocessor. We make use of 0.25?滋m CMOS technology synthesis and make layout. Post-simulation and emulation with CPLD indicate that the microprocessor is normal to run.
出处
《微电子学与计算机》
CSCD
北大核心
2004年第6期45-48,共4页
Microelectronics & Computer
基金
总装备部项目(0105TJ003)
