摘要
VLSI的时延优化问题是设计高性能的VLSI的重要问题。本文提出了在VLSI布图的版图规划中优化单元内时延的方法，并首先导出路径时延与单元面积的关系，从而运用数学规划方法得到优化了的单元面积。结果表明，这是一个有效的单元代化方法。
The optimizing of cell delay of VLSI is an impnortant issue in designing high perforMance VLSI. Amethod is presented in this paper for optimizing cell delay in foorplanning For VLSI. At first. the relationship between path delay and cell area has been deduced. Then Call areas are obtained by means of mathematical programming. The result shows that is An efficient optimizing method.
出处
《杭州电子工业学院学报》
1994年第2期1-6,共6页
Journal of Hangzhou Institute of Electronic Engineering
基金
国家"八.五"攻关项目
