摘要
介绍一种基于V HDL 的采用自顶而下(up to bottom)设计方法实现的数字频率计。该设计方法与传统的设计方法相比,具有外围电路简单,程序修改灵活和调试容易等特点。特别是在设计的初期阶段可以通过软件仿真来预知设计方案的可行性,便于及时的调整设计方案,避免了传统方法中到项目开发的后期才发现方案不妥,从而造成人力、物力的浪费。同时,在本设计中用到的CPL D器件运行稳定可靠,可反复擦写,便于系统的维护与更新。
The design method,which realizes digital frequency counter of up to bottom based on VHDL is introduced.Comparing with traditional design method,this design method has characteristics of simple peripheral circuit,easy modificative procedure and debugs,etc.Especially it can come and foresee feasibility of the design project through the software way to imitate the true mode in the design′s early stage,benefit the prompt adjustment of the design project,and avoid finding the project improper thus causes the emergence of such a situation of waste of the manpower and materials until what the project is developed later stage in the traditional method.Meanwhile,CPLD device which is used in the design runs steady and reliable,and can be erased and written repeatedly,it also benefits systematic maintenance and update.
出处
《现代电子技术》
2005年第15期102-104,共3页
Modern Electronics Technique
基金
广西大学设备处实验课独立设课项目"电子技术实验"序号 :1 0
广西教育科学"十五"规划重点资助课题"电子技术实验教学改革研究"(2 0 0 1 A0 1 3)
广西教育科学"十五"规划课题"电子技术实验教学新体系的探讨" (2 0 0 3B1 5)
