摘要
基于可复用的嵌入式IP内核模块的系统级芯片(SoC)设计方法使测试面临新的挑战。文章针对IP内核模块测试所面临的技术难点,介绍了IP核模块实现测试所需要构建的硬件环境和通用结构,并以嵌入ARM微处理器核的SoC为例,提出了具体的测试解决方案。
The system-on-chip（SoC） based on reusable embedded IP（intellectual property） cores pose new challenge for test. A novel test methodology is described in this paper along with its structure. A typical system on chip（SoC） test carried out at ARM is also presented as a case study.
出处
《微电子学与计算机》
CSCD
北大核心
2005年第10期66-69,共4页
Microelectronics & Computer
