摘要
高速、高精度数字脉压处理器的设计与实现是现代雷达系统的关键技术之一。针对FPGA实现的定点脉压处理器数据动态范围小、处理精度低的缺点,提出并实现了一个高性能浮点脉压处理器。文中重点阐述了自定制浮点数据格式的确定、浮点运算的FPGA实现及处理器硬件实现等关键技术。该处理器已投入使用,工作性能稳定,系统时钟80 MHz,能在140μs时间内完成1 024点信号的脉压,处理误差小于-60 dB,功耗小于5 W。
Design and realizaton of digital pulse compression processor with high speed and good precision is one of the key techniques of modern radar system. In this paper,the realization of a floating-point pulse compression processor with FPGA is proposed to overcome the problem of small dynamic range and low precision of a fixed-point processor. The key techniques of the definition of the floating-point format , the FPGA implementing of floating-point operation and the hardware realization of processor are discussed. Such a processor has been put into service and showed stable performance. Its operating frequency is 80 MHz and it can finish pulse compression of 1024 points signals in 140μs with error consumption less than -60 dB and power consumption less than 5 W.
出处
《现代雷达》
CSCD
北大核心
2005年第10期41-44,共4页
Modern Radar
关键词
脉冲压缩
现场可编程门阵列
快速傅里叶变换
pulse compression
field programmable gate array
fast Fourier transform
