摘要
基于绝热开关或能量恢复技术,提出了应用于低功耗系统的主从型绝热D触发器、SR触发器和JK触发器设计.所提出的这些电路工作于二相正弦功率时钟,这有助于降低功率时钟电路的设计难度.通过接入两个与功率时钟相连的弱nMOS管解决了输出悬空态问题.电路采用传输开关作为逻辑输入模块,消除了接地端,因而具有更低的能耗.应用绝热JK触发器,并以十进制加法计数器为例演示了能量恢复型时序电路的设计.通过采用0.5μm互补金属氧化物半导体(CMOS)工艺参数的集成电路模拟程序(SPICE)模拟,结果验证了该触发器较之以往的设计具有更低的功耗.
Based on the adiabatic switching or energy recovery technique, some master-slave flip-flops including D, SR and JK flip-flops were presented as candidates for low power applications. These flip-flops employed two-phase sinusoidal power clock. The problem of floating output nodes was solved by connecting two weak nMOS transistors to the power clock. The proposed flip-flops utilized pass transistor functional blocks to eliminate the path to ground and thereby achieved higher power saving. A decade counter was used to illustrate the design of energy recovery sequential circuit using the proposed JK flip-flops. The designed circuits was simulated by simulation program with integrated circuit emphasis （SPICE） using 0.5μm complementary metal oxide semiconductor （CMOS） technology. The simulation results show that the proposed flip-flop＇s, power consumption is less than that of conventional CMOS transmission gate-based flip-flops and the PAL-2N-based flip-flops.
出处
《浙江大学学报（工学版）》
EI
CAS
CSCD
北大核心
2005年第10期1545-1548,共4页
Journal of Zhejiang University：Engineering Science
基金
国家自然科学基金资助项目(60273093)
