摘要
针对在VHDL语言课程教学中,如何设置数字电路设计中的数据对象的若干教学问题进行了探讨。文中首先论述了VHDL语言的数据对象的一些基本概念;重点阐述了在教学中如何通过实例使学生能够分清VHDL语言的信号与变量这两个极易混淆数据对象的使用区别;同时,指出了在应用其进行设计过程中应注意的一些问题。从几次的教学效果来看,本文提出的方法对VHDL语言教学,以及VHDL设计都具有一定的指导意义。
This paper gives some discussion about teaching experience in setting data objects in digital circuit designing during teaching VHDL project. Basic concepts about data objects in VHDL are given first; then the paper focuses on the method to demonstrate the difference between two confusable VHDL objects, sig- nal and variable, by some examples prepared for students in teaching; after that, some problems in circuit designing using VHDL are pointed. Based on our experience, the method given in this paper has positive effect on VHDL teaching and designing.
出处
《电气电子教学学报》
2006年第3期30-32,35,共4页
Journal of Electrical and Electronic Education
