摘要
本文采用套筒式级联增益自举电路,设计了一种用于高速、高分辨率ADC的CMOS全差分运算放大器,达到了高增益、低功耗的设计目标。在3.3V电源电压下,基于TSMC0.35μm CMOS工艺模型,本设计驱动1pF负载时,相位裕度为65°,单位增益带宽为320MHz,功耗5.7mW,压摆率为200V/μs。
The paper adoptsg ain-boostedt elescopic cascadec ircuit,d esignsa f ully differentialC MOSo perationala mplifierf orh igh-speed andh igh-resolvingADC, and achieves the design objective of high dc-gain and low power. With the 3.3V power supply and TSMC 0.35μm CMOS process model, thephase margin of this OTA is 65 with 1pF load, the unity gain bandwidth is 320MHz, and the power consumption is 5.7mW.
出处
《电子设计应用》
2007年第2期57-59,10,共3页
Electronic Design & Application World
