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约束输入精简的多扫描链BIST方案 被引量：15

Constraint Input Reduction BIST Scheme for Multiple Scan Chains
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摘要 运用有约束的输入精简、LFSR编码与折叠计数器技术,实现了对确定性测试集的压缩与生成.其主要优点是将多种测试方法有机地结合在一起,充分地发挥了各种方法在压缩测试数据方面的优势.与国际上同类方法相比,该方案需要的测试数据存储容量更少,测试应用时间明显缩短,总体性能得到提升;并且能够很好地适应于传统的EDA设计流. Constrained input reduction, LFSR coding and folding counter are applied to compress and generate a deterministic test set. Its highlight is effectively combining previous several test methods and taking full advantage of the methods in test data compression. Compared to international similar approaches, the proposed scheme needs less storage volume, can reduce testing time significantly, fully upgrade test performance, and is compatible with traditional scan-based design flow.
作者 梁华国 刘军 蒋翠云 欧阳一鸣 易茂祥
机构地区 合肥工业大学计算机与信息学院 合肥工业大学理学院
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2007年第3期371-375,共5页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金(90407008) 国家自然科学基金重点项目(60633060) 安徽省自然科学基金(050420103)
关键词 内建自测试 输入精简 线性反馈移位寄存器 折叠计数器 多扫描链 测试数据压缩 built-in self-test （BIST） input reduction linear feedback shift register （LFSR） folding counter multiple scan chains test data compression
分类号 TP206.1 [自动化与计算机技术—检测技术与自动化装置]
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参考文献13

  • 1Wunderlich H J.BIST for systems-on-a-chip[J].Integration,the VLSI Journal,1998,26(1/2):55-78
  • 2Touba N A,McCluskey E J.Altering a pseudo-random bit sequence for scan-based BIST[C]//Proceedings of IEEE International Test Conference,Washington D C,1996:167-175
  • 3Jas A,Krishna C V,Touba N A.Weighted pseudo-random hybrid BIST[J].IEEE Transactions on Very Large Scale Integration Systems,2004,12(12):1277-1283
  • 4Liang Huaguo.A new technique for deterministic scan-based built-in self-test (BIST)[M].Aachen:Shaker Verlag,2003
  • 5梁华国,聚贝勒.海伦布昂特,汉斯-耶西姆.冯特利希.一种基于折叠计数器重新播种的确定自测试方案[J].计算机研究与发展,2001,38(8):931-938. 被引量：44
  • 6梁华国,蒋翠云.使用双重种子压缩的混合模式自测试[J].计算机研究与发展,2004,41(1):214-220. 被引量：38
  • 7梁华国,方祥圣,蒋翠云,欧阳一鸣,易茂祥.一种选择折叠计数状态转移的BIST方案[J].计算机研究与发展,2006,43(2):343-349. 被引量：12
  • 8McCluskey E J.Verification testing-a pseudoexhaustive test technique[J].IEEE Transactions on Computer,1984,C-33(6):541-546
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  • 10Li L,Chakrabart K.Test data compression using dictionaries with fixed-length indices[C]//Proceedings of IEEE VLSI Test Symposium,Napa Valley,CA,2003:219-224

二级参考文献33

  • 1[1]M Abramovici, M Breuer, A Friedman. Digital Systems Testing and Testable Design. New York: Computer Science Press, 1990
  • 2[2]K-T Chen, C-J Lin. Timing driven test point insertion for full-scan and partial-scan BIST. The IEEE Int'l Test Conf, Washington, D C, 1995
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  • 7[7]C Dufaza, G Cambon. LFSR based deterministic and pseudo-random test pattern generator structures. European Test Conference, Munich, 1991
  • 8[8]S Hellebrand, J Rajski, S Tarnick .et al.. Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers. IEEE Trans on Computers, 1995, 44(2): 223～233
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  • 10[10]S Hellebrand, H-J Wunderlich, A Hertwig. Mixed-mode BIST using embedded processors. Journal of Electronic Testing Theory and Applications (JETTA), 1998, 12(1/2): 127～138

共引文献60

同被引文献136

引证文献15

二级引证文献38

计算机辅助设计与图形学学报
2007年 第3期

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