摘要
介绍了用于WLAN802.11a收发信机的PLL频率综合器中可编程分频器的设计。基于ARTISAN标准单元库对可编程分频器进行了设计,详细介绍了自定义线负载模型、版图规划、时钟树综合、布局布线、静态时序分析等VLSI设计流程,并通过前端和后端设计的相互协作对电路进行了反复优化。最后给出了可编程分频器的后仿真结果、芯片照片和测试结果,芯片内核面积1360.5μm2,测试结果表明设计符合要求。
As the scale of integrated circuit enlarges and the speed increases, the design based on DSM process has experienced a rapid development. This article, taking programmable frequency divider as an example, introduces the back-end design process based on the DSM standard cell. Further more, the procedure, which includes initial synthesis, timing driven placement, clock tree synthesis, static timing analysis （STA）, post-layout optimization and so on, are discussed elaborately. Finally, the layout is displayed and taped out in TSMC 0.18μm CMOS technology. The test results indicate that the design complies with the design requirement.
出处
《微电子学与计算机》
CSCD
北大核心
2007年第5期61-65,共5页
Microelectronics & Computer
基金
国家自然科学基金项目(60472057)
关键词
可编程分频器
频率综合器
标准单元
CMOS
programmable frequency divider
frequency synthesizer
standard cell
CMOS
