摘要
通常的Verilog HDL编码风格生成的电路速度慢、面积大、毛刺干扰严重.基于此特点提出一种优秀、高效的Verilog HDL描述方式来进行有限状态机设计,介绍了有限状态机的建模原则,并通过一个可综合的实例,验证了该方法设计的有限状态机在面积和功耗上的优势.
The circuits generated from the common Verilog HDL ceding style are slow in speed, big in area, and serious in burr interference. Based on these characteristics, this paper presents an excellent and efficient manner described in Verilog HDL in the design of finite state machine. In addition, it introduces the modeling of finite state machines, and verifies with a synthesizable example the advantages of the design method of finite state machine in the area and power consumption. This method has a certain guiding significance in the design of very large scale integrated circuits.
出处
《重庆工学院学报》
2007年第9期55-58,共4页
Journal of Chongqing Institute of Technology
基金
重庆市自然科学基金资助项目(渝科发技字[2004]55)
