摘要
介绍异步FIFO的基本结构和工作原理,分析异步FIFO的设计难点及其解决办法,在传统设计的基础上提出一种新颖的电路结构,用verilog描述并对其进行综合仿真并在FPGA上实现,得到较好的性能。
This article introduces the basic structure and the principle of work of asynchronous FIFO, then analysis it’s design difficulty and its solution, and proposes one kind of novel electric circuit structure base on the traditional design , finally uses verilog hardware describe language to describe,carries on the synthesis simulation and realizes on FPGA, obtained a better performance.
出处
《计算机与数字工程》
2007年第6期191-194,共4页
Computer & Digital Engineering
