摘要
提出了一种基于现场可编程逻辑器件(FPGA)的有限冲击响应(Finite Impusle Response, FIB)滤波器的设计新方法,该方法利用分布式算法来并行实现FIR数字滤波器硬件电路,并用VHDL编程。仿真实验结果表明,该方法能使设计简单、灵活,同时利用加法器代替乘法器不仅节约了硬件资源,而且提高了数字信号处理的速度。
The paper introduces the new scheme design of FIR fiher based on FPGA. The hardware of the digital FIR filter is implemented with the distributed arithmetic, programmed with VHDL language. The experiment results indicate that the approach is feasible, and it can make the design easier. It not only saves the resource of hardware, but also raises the speed of digital signal processing by using adder as a substitute for multiplier.
出处
《信息与电子工程》
2007年第5期388-390,共3页
information and electronic engineering
