摘要
FFT速度的提高是数字信号处理领域中的核心问题,并行流水计算是实现大规模FFT高速计算的基本技术.在分析了基二时间抽取算法并行计算时输入数据的地址特性后,提出了二维SRAM的设计,它突破了并行计算N点FFT时普通SRAM地址非线性变化的瓶颈,达到N个蝶形单元并行流畅读写计算数据的目的,并使得数据地址数量变少,生成简单.对一个8×8字单元,每个字16bit的二维SRAM进行设计仿真,可以验证其功能正确.
The increase of FFT computing speed is the main subject in the realm of digital signal processing. Parallel computing and pipeline structure are the basic technologies to achieve high speed of large scale FFT computing. After analyzing the address of computing data in radix-2 decimation-in-time FFT algorithm, we design a two-dimension SRAM. The non-linear changing of data address, which is the bottleneck when using normal SRAM to compute an N-point FFT, can be removed. √N butterfly units in FFT can compute fluently in parallel. The amount of simplified data address can be decreased largely. An 8 by 8 words, 16 bits word length, two-dimension SRAM is designed and simulated, the function is verified .
出处
《中国科学院研究生院学报》
CAS
CSCD
2008年第1期123-128,共6页
Journal of the Graduate School of the Chinese Academy of Sciences
关键词
FFT
基二时间抽取算法
二维SRAM
并行计算
FFT, radix-2 decimation-in-time FFT algorithm, two-dimension SRAM, parallel computing
