摘要
介绍了一种基于FPGA(现场可编程门阵列)的全数字锁相环设计方法与性能研究,详细叙述了基于FPGA的全数字锁相环系统的硬件设计构成和软件构建思路,并运用VHDL硬件描述语言实现了全数字锁相环系统,给出了电路系统的仿真结果.通过仿真结果对锁相环系统进行了简要的性能分析.
The design method and the performance research of an entire digital phase-lock loop is introduced based on the FPGA, the hardware structure and the software construction thought of entire digital phase-lock loop system are described depending on the FPGA in detail. The system of entire digital phase-lock loop with VHSIC Hardware Description Language is realized, and the circuit software simulation result is given. According the simulation result, the phase-lock loop system is analyzed briefly.
出处
《光电技术应用》
2007年第6期63-66,共4页
Electro-Optic Technology Application
