摘要
在FPGA硬件实现多通道信号处理的过程中,为了减少占用的FPGA硬件资源,降低设备的研制和生产成本,本文提出了一种多通道信号处理复用结构,并给出了该复用结构的调度机制以及在实现过程中遇到的速率匹配、处理速度、复用通道数、硬件资源等问题的解决方法。实践表明,当运用Altera公司的StratixII器件时,32个通道信号处理复用结构在增加FPGA器件的寄存器资源占用量18.2%情况下,能够减少ALM资源占用量94.3%。
This paper presents a muhiplexing-architecture and its realization method using FPGA （Field Progammable Gate Array） to decrease the used FPGA hardware resources （mainly ALM resources） and decrease the operating costs and research costs in application of multi-channel signal processing. The task scheduler of the multiplexing-architecture is given concretely. Some methods that solve speed-matching, multiplexing channel numbers and hardware resources in the realization process axe given too. Practice show that using Stratix II device from Altera Corporation, the multiplexing-architecture of 32-channel signal processing can be decreased 94. 3 percent of ALM （Adaptive Logic module） resources while increasing 18. 2 percent register resources.
出处
《电子测量与仪器学报》
CSCD
2008年第1期72-75,共4页
Journal of Electronic Measurement and Instrumentation
关键词
复用结构
并行结构
多通道信号处理
现场可编程门阵列
调度机制
multiplexing-architecture； parallel-architecture； multi-channel signal processing； FPGA； task scheduler
