摘要
为了解决标清数字视频的帧同步器中的帧缓冲器设计问题,文中描述了一种可以支持实时数据流处理的高速大容量FIFO设计方法。该方法用SDRAM做为存储体,用FPGA设计双口SDRAM状态机控制SDRAM工作,并在FPGA内部实现数据接口同步,对数据流进行流水线式处理,完成数据的无缝缓冲,保证输入输出数据流的连续性。通过下载调试,该FIFO设计方法可用做视频帧同步器中的帧缓冲器。
This paper presents a new design of high speed and deep FIFO which supports real time data flow processing. The design is implemented with deep FIFO as frame storage of standard digital video signals, SDRAM as storage device and FPGA as SDRAM controller. The data interface synchronization block is also designed to issue the sequentiality of input and output data flow.
出处
《电子科技》
2008年第6期1-3,8,共4页
Electronic Science and Technology
