摘要
介绍了FIR(有限冲击响应)数字滤波器的原理、结构和设计方法,运用Verilog HDL语言,在CycloneⅢ芯片(EP3C25F324C8NES)上,实现16阶分布式算法的FIR数字滤波器电路的设计。分布式算法FIR数字滤波器是基于ROM查找表,能够极大地减少硬件电路规模,实现流水线处理,提高电路的执行速度。16阶分布式算法的FIR数字滤波器所占CycloneⅢ芯片的资源小于1%,这给在同一块CycloneⅢ芯片上,实现滤波器与其它FPGA设计的综合提供了宽广的发展空间。
First, we describe the principle, structure and design of FIR digital filter in this paper. Then we realize a 16 order distributed FIR digital filter which purpose is to realize multiplication and addition. The distributed FIR digital filter is based on ROM look-up table. It can reduce the scale of hardware circuit greatly and realizes the design of assembly line. It improves the speed of execution. At last, the innovation of this paper is that it realizes the 16 order distributed FIR digital filter based on CycloneⅢ with the hardware describing language of Verilog HDL on the large-scale integrated circuit. The resource of Cyclone Ⅲ chip is used less then 1% by the 16 order distributed FIR digital filter. This provides extensive space for development of other FPGA designs on the same CycloneⅢ chip.
出处
《信息化研究》
2009年第2期15-18,51,共5页
INFORMATIZATION RESEARCH
基金
虚拟地理环境教育部重点实验室开放项目(1640703041-5)
