摘要
本文主要研究了用FPGA芯片内部的EBRSRAM来实现异步FIFO设计方案,重点阐述了异步FIFO的标志信号——空/满状态的设计思路,并且用VHDL语言实现,最后进行了仿真验证。
This article mainly studied the scheme usage of the internal resources EBRSRAM of FPGA realizes asynchronous FIFO,Focused on method of the Signal signs empty/ full state,And realizes with the VHDL language, finally has carried on the simulation confirmation.
出处
《微计算机信息》
2009年第20期153-155,共3页
Control & Automation
基金
河南省自然科学基金(No.072300410180)
省高校科技创新人才基金(No.2008HASTIT029)
