摘要
通过分析异步FIFO的基本结构和工作原理,以降低亚稳态的出现频率、充分利用异步FIFO的内存资源为主要目的,提出一种在FPGA内部实现的异步FIFO设计方法。本文在传统设计的基础上提出一种新颖的电路结构来准确判断空/满标志位的产生,即检测加计数器的方法;并用QuartusII对其进行仿真,得到了比较好的性能。
The basic structure and principle of asynchronous FIFO are introduced. In order to reduce the probability of metastability and to take full advantage of the memory resources in the asynchronous FIFO,a method which implements asynchronous FIFO inside of FPGA is proposed. A novel circuit based on traditional circuit is given to judge accurately the full/empty flag by detecting the up counter. Simulation result in QuartusⅡ shows that the system has good performance.
出处
《单片机与嵌入式系统应用》
2009年第8期33-35,共3页
Microcontrollers & Embedded Systems
