摘要
利用一种新技术,在低压(1.8 V)条件下,设计了一种高性能的开关电流(SI)存储单元电路。该电路通过在基本存储单元基础上增加一个电压反转跟随器电路(FVF),从存储晶体管的输入端直接消除时钟馈通(CFT)误差电压,从而阻止了电流误差的产生,使得输出端的CFT误差电流降为原来的6%,并通过Hspice给出了仿真结果。结果表明所设计的电路方案正确有效。
A high performance switched-current memory cell is designed with low supply voltage (1.8 V), using a new type of technology. It adds a FVF circuit based on the primary circuit, which can remove clock feedthrough voltage from the input port of the memory transisitor directly. As a result, the current error at the output is decreased to 6 %. Simulation results with Hspice are given. The result shows that the designed circuit is correct and effective.
出处
《电子器件》
CAS
2009年第6期1077-1079,1083,共4页
Chinese Journal of Electron Devices
基金
广西科学研究与技术开发计划项目资助(0731021)