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一种基于伪布尔可满足性FPGA布线算法 被引量:1

An FPGA Routing Algorithm Based on Pseudo-Boolean Satisfiability
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摘要 为了克服布尔可满足性算法在现场可编程门阵列布线中存在的不足,引进了一种在标准对称阵列(隔离岛状)现场可编程门阵列结构下的新型有效布线方法——伪布尔可满足性算法,并结合实例详细地阐述了将其应用于布线的原理及方法,同时采用实际工业电路将布尔可满足性算法与伪布尔可满足性算法作出比较。实验结果显示,伪布尔可满足性算法比布尔可满足性算法在布线时间上减少了10.5%,在稳定性上提高了3.3%。 To overcome shortcomings of the Boolean Satisfiability Algorithm in the Field Programmable Array routing process, a new and efficient routing method, the Pseudo-Boolean Satisfiability Algorithm, has been introduced for a standard symmetrical array (Island-style) Field Programmable Gate Array. The principle and the method of applying this algorithm to routing are also explained by the detailed example. Furthermore, practical industrial circuits are used to compare the effects of the two algorithms. Results indicate that the Pseudo-Boolean Satisfiability Algorithm can save the muting time by 10.5% and improve the stability by 3.3% than the Boolean Satisfiability Algorithm.
出处 《微计算机信息》 2010年第2期125-127,共3页 Control & Automation
关键词 现场可编程门阵列 布尔可满足性 伪布尔可满足性 布线 FPGA Boolean Satisfiability Pseudo-Boolean Satisfiability Routing
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参考文献8

  • 1刘战,须自明,王国章,于宗光.一种基于迷宫算法的有效FPGA布线方法[J].微计算机信息,2007,23(17):207-208. 被引量:2
  • 2Lucent Technologies. Field-Programmable Gale Arrays Data Book[M]. New Jersey: Lucent Technologies, 1996.
  • 3A. Aggarwal, D. Lewis. Routing Architectures for Hierarchical Field-Programmahle Gate Arrays [C]. Proceedings of the 1994 IEEE International Colfference on Computer Design: VLSI in Computer & Processors, Washington DC: IEEE Computer Society, 1994: 475-478.
  • 4C. Lee. An Algorithm for Path Connections and its Applications [J]. IRE Transactions on Electronic Computers, 1961,10: 346-365.
  • 5L. McMurchie. C. Ebeling. PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs [C]. International Symposium on Field Programmable Gate Arrays, Monterey, CA: ACM 1995: 111-117.
  • 6B. W. Kernighan, S. Lin. An Efficient Heuristic Procedure for Partitioning Graphs [J]. Bell Systems Technical J., 1970, 49: 291-307.
  • 7J. S. Swartz, V. Betz, J. Rose. A fast routability driven router for FPGAs [C]. The 6th International Workshop Field-Programmable Gate Arrays, Monterey, CA: ACM 1998, 5: 140-149..
  • 8P. Barth. A Davis-Putnam based Enumeration Algorithm for Linear Pseudo-Boolean Optimization[R]. Technical Report MPI-I- 95-2-003, Saarbrucken,Germany: Max Ptanck Institut Fur Informatik, 1995.

二级参考文献7

  • 1杨守良.Matlab/simulink在FPGA设计中的应用[J].微计算机信息,2005,21(08Z):98-99. 被引量:26
  • 2C.Lee.An Algorithm for Path Connections and its Applications.IRE 7Fansactions on Electronic Computers,Sept.1961.
  • 3L.McMurchie and C.Ebeling.PathFinder:A Negotiation-Based Performance-Driven Router for FPGAs.In Interantional Symposium on FieldProgrammable Gate Arrays,Monterey,Ca.,Feb.1995.
  • 4G.W.Clow.A Global Routing Algorithm for General Cells.In Proceedings,ACM/IEEE 21,51Design Automation Conference,1984.
  • 5J.Swartz,V.Beta,and J.Rose.A Fast Routability-Driven Router for FPGAs.In 6th International Workshop on Filed-Programmable Gate Arrays,Monterey,Ca,Fleb.1998.
  • 6N.J.Nilsson.Principles of Artificial Intelligence.Tioga Publishing,Palo Alto,Ca.,1980
  • 7L.hlcAfurchie and C.Eheline.PathFinder:A NeentiationBased Perforrruanre-Driven Router for FPGAS.In International Symposium on Field Programmable Gate Arrays.Monterey,Ca.,Feb,1995.

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同被引文献5

  • 1雷绍充,邵志标.VLSI测试方法学和可测性设计[M].电子工业出版社.
  • 2钟汝刚 邝继顺 肖媛.基于FPGA的故障模拟器设计与实现.中国科技在线,2009,.
  • 3Amin M B,Vinnakota B.Data parallel fault simulation.IEEE Trans. On Very Large Scale Integration (VLSI) Systems,1997,7(2):183-190.
  • 4Jin-Hua Hong, Shih-Am Hwang. An FPGA-based Hardware Emulator for Fast Fault simulation. IEEE Trans. on Circuits and Systems, 1996, 11(4): 354 - 348.
  • 5杨士元.数字系统的故障诊断与可靠性设计[M].清华大学出版社.2002.4.6-7.

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