摘要
提出了基于FPGA的抗混叠FIR数字低通滤波器的设计与实现.利用Matlab和FDATool设计并确定FIR滤波器的系数,通过Altera DSP Builder和Matlab/Simulink完成滤波器模块的设计和仿真,DSP Builder可将设计好的滤波器模块直接转换成在FPGA上实现滤波器所需的VHDL语言,并在Quartus Ⅱ平台上进一步完成该滤波器的仿真和FPGA实现.最后对叠加有混叠频率成分的的电网电压信号进行滤波仿真,结果表明,滤波器符合设计要求.这种利用DSP Builder将Matlab和Quartus Ⅱ设计工具结合起来进行FIR数字滤波器设计的方法简单有效,所生成的滤波器模块可移植性好.
An anti-aliasing low-pass FIR Digital Filter based on FPGA is designed and implemented. The parameters of FIR Filter is designed through MATLAB and FDATool. The filter model is designed and simulated by using Altera DSP Builder and Matlab/Simulink. The DSP Builder can convert the designed filter model into VHDL language directly which is needed to realize the filter on FPGA and the filter is simulated and implemented under FPGA on the Quartus Ⅱ platform. Finally, in simulation experiments, the signal of power line voltage with the aliasing frequency components superimposed is as the input of the designed filter and the results of simulation show that the filter satisfies the design requirement. Using DSP Builder, the method to design the FIR Filter hy combining Matlab/Simulink and Quartus Ⅱ design tools together well is simple and effective. This kind of filter model has good portability.
出处
《浙江工业大学学报》
CAS
北大核心
2010年第2期192-196,共5页
Journal of Zhejiang University of Technology
