摘要
设计了一种适用于高速CMOS图像传感器中积分器阵列的采样保持电路。在采样保持电路的保持路径中采用一种抑制衬底偏压效应的T型开关,取代传统的CMOS传输门开关,可以抑制衬底偏压效应带来的阈值变化,保证开关导通电阻的线性度,同时由于在开关设计中引入了T型结构,减少高速输入下寄生电容引入的信号馈通效应,可以实现更为优化的关断隔离。基于SMIC(中芯国际)0.13μm标准CMOS工艺设计了一个适用于高速采样积分器阵列中的CMOS采样保持电路。Cadence Spectre仿真结果表明在输入信号达到奈奎斯特频率时,电路信噪失真比(SINAD)达到了85.5dB,无杂散动态范围(SFDR)达到92.87dB,而功耗仅为32.8mW。
A sample-and-hold circuit utilized in high speed integrator array is designed. The integrator array is an important part of CMOS image sensor. In this paper, a new T type switch which can restrain the substrate biasing effect is designed to replace the traditional CMOS transmission gate switch. Thus, the linearty of the switch’s turn-on resistance can be assured due to the changes of threshold voltage caused by the substrate biasing effect is limited. Also, this new T type structure can reduce the charge feed through effect when the input signal is high. Based on SMIC 0.13 μm Standard CMOS technique, an sample-and- hold circuit applicable to the CMOS image sensor is designed. Spectre simulation results show that the Signal-to-Noise And Distortion Ratio and Spurs Free Dynamic Range is 85.5dB and 92.87dB respectively under the Nyquist input frequency, the whole chip consumes only 32.8mW.
出处
《传感技术学报》
CAS
CSCD
北大核心
2010年第7期963-967,共5页
Chinese Journal of Sensors and Actuators
关键词
图像传感器
衬底偏压抑制T型开关
积分器阵列
采样保持电路
image sensor substrate biasing effect attenuated T switch
integrator array
sample-and-hold circuit
