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Multiple bit upsets mitigation in memory by using improved hamming codes and parity codes 被引量：1

Multiple bit upsets mitigation in memory by using improved hamming codes and parity codes
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摘要 This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes. This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes.
作者 祝名 肖立伊 田欢
机构地区 Microelectronics Center National Key Laboratory of Science and Technology on Reliability Physics and Application Technology of Electrical Component
出处 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2010年第5期726-730,共5页 哈尔滨工业大学学报（英文版）
基金 Sponsored by the Opening Project of National Key Laboratory of Science and Technology on Reliability Physics Application Technology of Electrical Component(Grant No.ZHD200903)
关键词 MEMORY multiple bit upsets improved hamming codes two-dimensional error codes memory multiple bit upsets improved hamming codes two-dimensional error codes
分类号 TN402 [电子电信—微电子学与固体电子学]
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参考文献14

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同被引文献19

  • 1冯彦君,华更新,刘淑芬.航天电子抗辐射研究综述[J].宇航学报,2007,28(5):1071-1080. 被引量：70
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  • 3Leray J L. Effects of atmospheric neutrons on devices, at sea level and in avionics embedded systems [ J ] Microelectronics Reliability, 2007, 47(9 - 11 ) :1827 - 1835.
  • 4Baumann R C. Radiation-induced soft errors in advanced semiconductor technologies [ J ]. IEEE Transactions on Device and Materials Reliability, 2005, 5(3) : 305 -316.
  • 5Cardarilli G C, Leandri A, Marinucci P, et al. Design of a fault tolerant solid state mass memory [ J ]. IEEE Transactions on Reliatility, 2003, 52(4): 476-491.
  • 6Kirn J, Hardavellas N, Mai K, et al. Multi-bit error tolerant caches using two-dimensional error coding [ C ]. 40th Annual IEEE/ACM International Symposium on Microarchitecture, Chicago, USA, December 197 - 209, 2007.
  • 7Naseer R, Draper J. Parallel double error correcting code design to mitigate multi-bi! upsets in SRAMs[ CI. 34th European Solid- State Circuits Conference, Edinburgh, U. K. , September 222 - 225, 2008.
  • 8Neuberger G, Kastensmidt D L. Multiple bit upset tolerant SRAM memory [ J ]. ACM Transactions Design Automation Electronic Systems, 2003, 8(4) : 577 -590.
  • 9Bajura M A, Boulghassoul Y, Naseer R, et al. Models and algorithmic limits for an ECC-based approach to hardening sub-100-rim SRAMs [ J]. IEEE Transactions on Nuclear Science, 2007, 54(4): 935-945.
  • 10Zhu M, Xiao L Y, Song L L, et al. New mix codes for multiple bit upsets mitigation in fault-secure memories [ J ]. Microelectronics Journal, 2011,42 (3) : 553 - 561.

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Journal of Harbin Institute of Technology(New Series)
2010年 第5期

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