摘要
在分析Sony公司ICX098BQ面阵CCD图像传感器驱动时序的基础上,对可调节曝光时间的CCD时序发生器及其硬件电路进行设计。选用FPGA器件作为硬件设计平台,使用VHDL语言对时序关系进行了硬件描述,采用Quartus Ⅱ 8.0对所设计的时序发生器进行了功能仿真,并以Altera公司的可编程逻辑器件为核心进行硬件适配。实际测试表明,所设计的驱动时序发生器能够满足面阵CCD的驱动要求,实现了设计目的。
In this paper,driving timing of Sony ICX098BQ area array CCD image sensor is analyzed.CCD timing generator with adjustable exposure time and its hardware circuit are designed.FPGA is chosen as the hardware design platform,and schedule generator is described with VHDL.The designed generator successfully fulfills function simulation with Quartus II 8.0 and fit into FPGA made by Altera.Actual tests show that driving schedule generator meets the driving requirement of area array CCD and achieves the design objectives.
出处
《电子科技》
2011年第6期127-130,133,共5页
Electronic Science and Technology
