摘要
高速数字分频器在基于锁相环的时钟产生电路中具有广泛的应用.在典型D触发器的基础上,文中提出了一种可响应6GHz输入时钟的改进型二分频结构,并实现了2～256连续分频的新型吞脉冲多模分频器.新型分频器结构简单并且不需要双模预分频单元,功耗和面积开销大幅度的降低.基于65nm CMOS工艺设计实现了该高速分频器,版图后仿真结果表明,分频器功能正确,且工作于6GHz时功耗不大于1.3mW.
High speed frequency divider is widely used in PLL--based frequency synthesizers. A configurable pulse --swallow divider with the range from 2 to 256 is presented in this article. The divider based on an improved divided --by--2 architecture without any conventional dual--modulus prescaler is designed to reduce power consumption and chip area. Implemented in 65nm CMOS process, post--layout simulation results show that the divider can work as high as 6GHz stably while the max power dissipation is no greater than 1.3mW.
出处
《微电子学与计算机》
CSCD
北大核心
2011年第11期1-4,9,共5页
Microelectronics & Computer
基金
国家自然科学基金项目(61070036)
