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An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling

An accurate analytical I-V model for sub-90-nm MOSFETs and its application to read static noise margin modeling
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摘要 We propose an accurate model to describe the I-V characteristics of a sub-90-nm metal-oxide-semiconductor field-effect transistor(MOSFET) in the linear and saturation regions for fast analytical calculation of the current.The model is based on the BSIM3v3 model.Instead of using constant threshold voltage and early voltage,as is assumed in the BSIM3v3 model,we define these voltages as functions of the gate-source voltage.The accuracy of the model is verified by comparison with HSPICE for the 90-,65-,45-,and 32-nm CMOS technologies.The model shows better accuracy than the nth-power and BSIM3v3 models.Then,we use the proposed I-V model to calculate the read static noise margin(SNM) of nano-scale conventional 6T static random-access memory(SRAM) cells with high accuracy.We calculate the read SNM by approximating the inverter transfer voltage characteristic of the cell in the regions where vertices of the maximum square of the butterfly curves are placed.The results for the SNM are also in excellent agreement with those of the HSPICE simulation for 90-,65-,45-,and 32-nm technologies.Verification in the presence of process variations and negative bias temperature instability(NBTI) shows that the model can accurately predict the minimum supply voltage required for a target yield. We propose an accurate model to describe the I-V characteristics of a sub-90-nm metal-oxide-semiconductor field-effect transistor (MOSFET) in the linear and saturation regions for fast analytical calculation of the current. The model is based on the BSIM3v3 model. Instead of using constant threshold voltage and early voltage, as is assumed in the BSIM3v3 model, we define these voltages as functions of the gate-source voltage. The accuracy of the model is verified by comparison with EISPICE for the 90-, 65-, 45-, and 32-nm CMOS technologies. The model shows better accuracy than the nth-power and BSIM3v3 models. Then, we use the proposed/-Vmodel to calculate the read static noise margin (SNM) ofnano-scale conventional 6T static random-access memory (SRAM) cells with high accuracy. We calculate the read SNM by approximating the inverter transfer voltage characteristic of the cell in the regions where vertices of the maximum square &the butterfly curves are placed. The results for the SNM are also in excellent agreement with those of the HSPICE simulation for 90-, 65-, 45-, and 32-nm technologies. Verification in the presence of process variations and negative bias temperature instability (NBTI) shows that the model can accurately predict the minimum supply voltage required for a target yield.
出处 《Journal of Zhejiang University-Science C(Computers and Electronics)》 SCIE EI 2012年第1期58-70,共13页 浙江大学学报C辑(计算机与电子(英文版)
关键词 MODELING NANO-SCALE Process variation Read static noise margin(SNM) SRAM Modeling, Nano-scale, Process variation, Read static noise margin (SNM), SRAM
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参考文献21

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