摘要
提出了一种基于有限状态机的增量式光电编码器接口电路设计方案。在光电编码器的1个脉冲周期中,通过对A,B两路信号电平变化进行细分,应用硬件描述语言实现状态机的设计。并在QuartusⅡ环境下进行编译与仿真,验证了设计的可行性。
In this paper, a finite state machine based on incremental photoelectrical encoder inter- face circuit design is proposed. In a photoelectric encoder pulse cycle,the design of state machine is realized using hardware description language, through the A, B two signal level changes were subdivided. And the feasibility of this design is verified in the software Quartus Ⅱ environment to compile and simulate.
出处
《机械与电子》
2012年第10期58-61,共4页
Machinery & Electronics
关键词
增量式光电编码器
有限状态机
硬件描述语言
FPGA
incremental photoelectrical encoder
finite state machine
hardware description language
FPGA
