摘要
针对基于改进型欧几里德(Modified Euclidean,ME)算法的RS码译码器所存在的不足,提出一种面积优化的欧几里德算法的FPGA实现方案.该方案充分利用改进型欧几里德模块的空闲资源,采用复用的方法将原先的2t个PE模块减少为t个.文章将该面积优化的欧几里德模块应用到RS(255,239)译码器的设计和实现中,以达到减少芯片面积,降低成本的目的.经过仿真和测试,基于此设计的高速并行RS译码器在正确实现译码功能的同时,可以大幅减少硬件资源的占用率,且其吞吐量达到6.4Gbps.
Aiming at the drawback of Modified Euclidean （ME） algorithm based RS decoder, this paper presents an area--efficient implementation of ME block using FPGA. Making full use of the idle resource of ME block, this implementation scheme adopts multiple structure by reducing the number of PE block from 2t to t. For reducing the hardware complexity and chip area, this paper applies this area--efficient ME block to the implementation of RS （255,239） decoder. Simulation and test result shows that the decoder based on this improvement can achieve the designed function and its throughput reaches 6.4Ghps while its hardware complexity is widely reduced.
出处
《微电子学与计算机》
CSCD
北大核心
2013年第2期21-24,共4页
Microelectronics & Computer
基金
中国空间技术研究CAST创新基金项目(CAST201016)
