摘要
详细介绍了在Xilinx Virtex-5系列FPGA中利用MIG2.0 IP核实现高性能的DDR2 Dual Rank内存条控制器的设计原理以及这种设计结构的独特性。针对实时数字信号处理系统需要大规模且高速的测试数据,以此平台为基础,在用户层实现了适合本应用背景的控制状态机。系统测试结果表明,该设计满足大容量存储和高速输出的要求。
This article elaborates the design principle of using MIG2.0 IP core in FPGA of Xilinx Virtex-5 series to realize the controller of DDR2 Dual Rank memory bank in high performance, which also mentions the uniqueness of this design structure. Based on this peafform, this system implements the control state machine in the user layer satisfying the application background that real-time digital processing system requires a large number of test data. The system test result reveals that this design meets the requirement of mass storage and high rate output.
出处
《电脑编程技巧与维护》
2013年第6期96-97,106,共3页
Computer Programming Skills & Maintenance
