摘要
针对UHF RFID系统中的并行循环冗余校验电路进行了设计和详细的分析。首先对基于经典的线性反馈移位寄存器的串行CRC电路进行了介绍,然后在串行CRC电路的基础上采用迭代法推导出了8位并行CRC电路。UHF RFID系统中采用了CRC-16的校验方法,因此该文着重以CRC-16为例,用Verilog HDL硬件描述语言设计实现了8位并行CRC-16电路,利用ALTERA公司的仿真工具Modelsim对其进行了功能仿真,最后在Quartus II 11.0开发环境下烧录到FPGA芯片上进行了板级验证。结果符合设计的初衷:一次处理1个字节的数据,且满足UHF系统通信速率的要求。
This paper proposes a parallel cyclic redundancy check（CRC） method to meet the high throughput requirements of ultra high frequency（UHF） system according to EPC global Class- 1 Gen- 2standard.We first introduce a serial CRC method based on the classical linear feedback shift register（LFSR）,and proposed a substitutional method to deduce the byte-wise parallel CRC circuit.Then this paper focuses on CRC- 16 as an example,implements byte- wise parallel CRC with Verilog HDL,verifies the validation by using Quartus Ⅱ 11.0 tool downloading to the FPGA device.It is found that the experimental results are consistent with the design,which shows that the circuit handles 1 byte data in a clock cycle and satisfies the requirements ofUHF system communication rate.
出处
《电子质量》
2014年第5期1-5,共5页
Electronics Quality
