摘要
基于子项空间共享技术,利用硬件描述语言编程,在FPGA上对FIR数字滤波器进行了实现。该设计将常系数乘法模块用加法和移位操作来实现,并利用子项共享有效地减少加法器个数。综合结果表明,所提方法可以有效节省硬件资源,降低实现成本,适用于低功耗数字系统设计。
FIR filters are realized on FPGA by using hardware description language programming based on sharing common subexpression. In these techniques, the coefficient multipliers are realized as a multiplier block （MB） with shared shifters and adders, and common subexpression sharing is used to effectively reduce the number of adders. The results of hardware synthesis show that the proposed method can efficiently save hardware resources consumption and achieve lower implementation costs, which is in favor of low-power design of digital systems.
出处
《电子技术应用》
北大核心
2014年第6期33-35,38,共4页
Application of Electronic Technique
关键词
FIR数字滤波器
子项空间
子项共享
FPGA
FIR digital filter design
subexpression space
common subexpression sharing
FPGA
