摘要
本文提出一种基于离散预约速率与分组长度组单元的公平队列调度器实现结构。该结构可根据不同预约速率需求 ,为其方便灵活的提供不同的预约带宽实现精度。组单元的模块化设计结构与流水线设计技术使得硬件逻辑资源得到更有效的利用。文中同时提出一种适用于该实现结构的定点时标重构技术 ,利用该技术可有效节约存储流时标的所需的外部存储空间。算法仿真与FPGA综合结果表明 ,该结构可支持 1 2Gbit/s的输出链路。通过有效的集成方式 ,该设计可进一步应用到端口速率为OC - 4 8( 2 4Gbps)
In this paper,we present an effective implementing architecture of packet fair queuing schedulers based on discrete backlogged rates and discrete packet lengths This architecture can flexibly provide different bandwidth granularities for various backlogged flow rates With the modularization design and pipeline technology,this architecture makes more efficient using of hardware resources We also provide a new technology of reconstructing flow timestamps for this architecture which can effectively decrease the storage space of timestamps Results of algorithm simulating and FPGA synthesizing show that this design can fully support a 1.2Gbit/s output link By the efficient combination of two 1 2Gbit/s schedulers,this design can be further capable of OC-48(2 4Gbit/s)operations in high speed routers
出处
《通信学报》
EI
CSCD
北大核心
2001年第4期1-7,共7页
Journal on Communications
基金
"8 63"计划通信技术主题子课题"边缘路由器研制"资助项目!( 863- 317- 0 1- 0 1- 0 2 - 99)
