摘要
设计一种应用于双系统卫星导航接收机射频前端芯片的CMOS小数分频锁相环频率合成器,它由压控振荡器、鉴频鉴相器、电荷泵、环路滤波器、分频器以及Σ-Δ调制器构成。设计基于SMIC0.18μm 1P6MRF CMOS工艺实现。后仿真结果表明,频率合成器输出频率范围约为1.1GHz^1.6GHz,锁定时间为9μs,具有良好的相位噪声性能,可为射频前端芯片提供本振信号。
A CMOS fractional-N PLL frequency synthesizer for the dual-system satellite navigation RF receiver is designed in this paper, which is composed of voltage controlled oscillator, phase and frequency detector, charge pump, loop filter , divider and sigma-delta modulator. The fractional-N PLL frequency synthesizer is implemented in a SMIC 0.18μm CMOS process. The simula- tion results show that the frequency of designed frequency synthesizer ranges from 1.1GHz to 1.6GHz, the settling time is 9μs and the performance of phase noise is good. The frequency synthesizer can be used in the RF receiver.
出处
《遥测遥控》
2015年第2期54-60,共7页
Journal of Telemetry,Tracking and Command
