摘要
随着高速通信系统的发展和传输速率的不断提高,锁相环作为提供精确时钟信号的核心电路,不仅需要产生低抖动、低噪声的时钟,而且要求频率覆盖范围广和支持多协议,而恒定带宽的锁相环无法满足多协议对锁相环带宽的要求。为了实现统一架构下多协议对不同频率的带宽要求,文中设计了一种宽温低抖动带宽自适应的锁相环电路,利用比较器模块和电荷泵形成反馈回路灵活地改变电荷泵电流,实现了环路带宽对不同频率在锁定过程中的自适应调整。同时采用改进的占空比校正、压控振荡器和电荷泵电路,降低了锁相环噪声。采用0.13μm CMOS工艺。测试结果表明输出频率为1.0625-3 GHz,数据率覆盖1.0625-5.9 Gbps,RJ〈1.3 ps,温度范围为-55-125℃,满足了FC-PI-4、PCIE1.1和Rapid IO1.3的协议要求,已成功应用于多款高速SerDes芯片中。
With the development of high speed communication system and the improvement of the transmission speed,PLL to be the core circuit of providing precision clock is not only required to produce low jitter and low noise clock,but also demanded wide frequency range and multi-protocol support,but the fixed bandwidth PLL cannot reach the requirement of multi-protocol. An adaptive bandwidth PLL with wide temperature range and low jitter is designed for achieving the requirements of multi-protocol in the unify configuration,using the comparator and charge pump to form a feedback loop to flexibly change the charge pump current,and making the loop bandwidth a-daptively adjusted at different rates. Adopt the improved duty-cycle controller,voltage control oscillator and charge pump circuit to de-crease the noise of PLL. This chip is fabricated in 0. 13 μm CMOS process. The measured results show that the output frequency is from 1. 062 5 to 3 GHz and the data rate covers 1. 062 5-5. 9 Gbps,RJ is less than 1. 3 ps,the operating temperature range is-55-125 ℃, which meet the protocol requirements of FC-PI-4、PCIE1. 1 and Rapid IO1. 3,and has been successfully applied to a variety of high speed SerDes chip.
出处
《计算机技术与发展》
2015年第6期163-165,175,共4页
Computer Technology and Development
基金
"十二五"微电子预研(51308010601
51308010711)
总装预研基金(9140A08010712HK6101)
关键词
锁相环
带宽自适应
宽温
低抖动
PLL
adaptive bandwidth
wide temperature range
low jitter
