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一种基于FPGA的开关中值滤波算法研究 被引量:8

Research on switching median filtering algorithm based on FPGA
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摘要 去除噪声是数字图像处理过程中的一个重要问题,对实时性要求高的系统而言,还要有足够的速度。文章基于现场可编程门阵列(field-programmable gate array,FPGA)处理图像并行特性,提出了一种适宜于FPGA实现的开关中值滤波算法,该算法利用求中值过程中计算所得的极值,通过比较极值起到开关作用;设计了开关中值滤波器的硬件架构,并对其进行仿真、分析和说明。Matlab仿真结果表明,该算法可以有效地去除图像的椒盐噪声,能更好地保护图像细节。 Denoising is an important issue during digital image processing, and high speed is indispensable when real-time characteristic of a system is needed strongly. Based on the parallel characteristic of field-programmable gate array(FPGA) when processing image, a switching median filtering algorithm which is suitable for FPGA implementation is proposed. This algorithm compares extremes which are calculated in the process of seeking the median smartly, and has a role of switching. The hardware structure of switching median filter is designed, and its simulation, analysis and illustration are given. The simulation results on Matlab show that the proposed algorithm can remove pepper salt noise from image effectively and keep the detail of image better.
出处 《合肥工业大学学报(自然科学版)》 CAS CSCD 北大核心 2016年第4期490-493,共4页 Journal of Hefei University of Technology:Natural Science
基金 中央高校基本科研业务费专项资金资助项目(J2014HGXJ0083)
关键词 图像处理 实时处理 中值滤波 现场可编程门阵列 去噪 digital image processing real-time processing median filtering field-programmable gatearray(FPGA) denoising
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