摘要
为了解决IRIG-B(AC)码解码精度低的问题,提高解调系统的稳定性,提出了一种利用高性能FPGA实现解调IRIG-B(AC)码的解码器。通过调用FPGA的IP核生成乘法器与FIR低通滤波器,将B(AC)码中的交流分量滤除掉,然后根据其幅值进行解调。该解码器能够快速准确地解调出IRIG-B(AC)码的时间信息,并输出与此时间信息对应的秒脉冲,通过输出端口将解调出的时间信息传输到上位机显示。通过大量试验证明该解码器准确度高、稳定性强,能够满足各种应用场所对IRIG-B(AC)码授时的要求。
In order to solve the IRIG-B（AC）decoding low accuracy problems and improve the stability of the demod-ulation system,a high-performance decoder is presented useing FPGA implementation demodulation IRIG-B（AC） codes.By calling the FPGA IP core generation multipliers and FIR low-pass filter,the AC components in the B（AC） code are filtered,then demodulated according to their amplitude.The decoder can demodulate time information of IRIG-B（AC）code accurately,transmit it quickly,and outputs the second pulse which is corresponding with time in-formation,through the output port to the demodulated PC display. Through extensive testing the decoder shows its accuracy,stability,and meets the requirements of various applications for IRIG-B（AC）code of timing.
出处
《电子器件》
CAS
北大核心
2016年第2期370-373,共4页
Chinese Journal of Electron Devices
基金
国家自然科学基金项目(61335008)
