摘要
压接式IGBT(press pack IGBT,PPI)器件在高压大电流应用领域中越来越引起关注。在PPI器件的开关过程中,内部并联芯片的最大电流过冲决定了器件的使用极限。该文提出了一种新型圆周凸台布局方式,可使PPI器件开通过程中各个IGBT芯片支路的电流过冲只超过额定电流的4.7%,各个续流二极管支路的电流完全一致。首先,采用Ansoft Q3D Extractor提取了PPI器件内部IGBT芯片发射极凸台支路和续流二极管并联凸台支路的电感参数矩阵,建立了用于分析PPI器件内部并联IGBT芯片和续流二极管支路开通与关断过程电流波形的等效电路,并基于实验测量方法,验证了所提电感参数的有效性。以2500V/600A的PPI器件为例,研究了该器件内部并联IGBT芯片和续流二极管支路的电流过冲及开关损耗特性。其次,基于该文定义的并联凸台支路的电流过冲系数和不均流因子,对现有的PPI器件内部凸台布局方式进行了优化。结果表明,优化后的凸台布局方式大大降低了PPI器件开通和关断过程中各个并联支路的电流过冲,且IGBT芯片的开关损耗更加均匀。该文的研究成果可以应用于更大电流参数的压接式IGBT器件内部并联芯片的布局设计。
The press pack IGBT has become much more attractive than ever due to its high voltage and high current ratings. In the switching process, the maximum current overshoot of paralleled chips inside PPI decides the application limit of the device. Based on Ansoft Q3D Extractor software, emitter copper pillars＇ inductances of paralleled IGBT chips and paralleled Diode chips in press pack IGBT were extracted; also the equivalent circuits were built to analyze the switching process. The effectiveness of the extracted inductance was verified based on experiments. Taking 2500V/600A press pack IGBT as an example, the current overshoot and the switching loss were analyzed. Based on the defined current overshoot factor and the non-uniform current distribution factor, the existed layout of copper emitter pillars was optimized. The results show that under the optimized layout, current overshoot in the switching process is greatly reduced; the distribution of switching losses of IGBT chips is much more consistent. At last, a circular layout of copper emitter pillars was proposed. The results of simulations show that, in. the switching on process, the maximum current overshoot of all IGBT chips is only 4.7% larger than the rated current value; and the currents of each Diode chios are always keep the same.
出处
《中国电机工程学报》
EI
CSCD
北大核心
2017年第1期233-243,共11页
Proceedings of the CSEE
基金
国家自然科学基金项目(51477048)
国家能源应用技术研究及工程示范项目(NY20150705)~~
关键词
压接式IGBT
瞬态电流分布
开关损耗
布局优化
press pack IGBT （PPI）
transient current distribution
switching loss
optimization of layout
