摘要
设计完成了一种基于FPGA的异步FIFO,运用Verilog HDL高级可编程语言和原理图相结合的设计方法实现FIFO读、写控制算法和数据查询、存储中断模块。运用时钟同步技术,解决了FIFO设计中亚稳态和竞争冒险的难点。最后采用Quartus II9.0设计仿真验证了该设计,测试结果表明该方案工作原理简单,性能稳定可靠。
A method of asynchronous FIFO is designed in this paper. The design method of Verilog HDL and schematic diagram is used to realize reading and writing method of FIFO, and data query and storage of interrupt module. The problems of metastable state and competitive risk are solved by using clock synchronization technology. Finally, the test results, by simulation of Quartus II9.0, show that it has a simple operational principle and stable performance.
作者
黄凡
Huang Fan(Naval Military Office Stationed at Kunming Area, Kunming 650051,China)
出处
《微处理机》
2017年第1期23-26,32,共5页
Microprocessors
