摘要
流量预测有利于实现网络资源的优化配置,而计算机技术的发展使得网络流量的变化特性十分复杂,通过以人工神经网络为主的智能算法进行预测已成为必然趋势。但人工神经网络的研究主要集中在算法层面,传统的硬件实现不易扩展和维护。为了改变人工神经网络串行预测特点不能满足实时处理要求,定制神经网络预测硬件不够灵活的现状,设计了一种采用分层可重构感知网络进行流量预测的方法。基于多核处理器中的片上网络技术构建并行感知器,通过修改分层感知网络结构,配置不同的激活函数实现可重构感知网络来进行流量预测,并在FPGA平台进行了仿真验证。测试结果表明,该方法灵活,且基于该方法的流量预测精度较高,实时性好。
Traffic prediction is helpful to optimize the allocation of network resources. With the development of computer technology ,the characteristic of network traffic is very complex, so it is an inevitable trend to forecast by using intelligent algorithms based on artificial neural network. However, the research of artificial neural network mainly focuses on the algorithm, traditional hardware implementation is not easy to expand and maintain. In order to change the situation that the artificial neural network can＇ t meet the requirement of real-time processing and customized neural network prediction hardware isn＇ t flexible enough, we design a method of traffic prediction based on hi- erarchical reconfigurable perceptron network, which is used for the traffic prediction by constructing parallel perceptron based on the on- chip network technology of the multi-core processors, modifying the hierarchical perceptual network structure and configuring different activation functions. Finally the simulation verification is carried out on the FPGA platform. Tests show that the method is flexible and has high prediction accuracy and good real-time performance.
作者
李莉
吴润泽
包正睿
庞思睿
LI Li;WU Run-ze;BAO Zheng-rui;PANG Si-rui(Economic and Technical Research Institute, State Grid Jibei Electric Power Company, Beijing 100055, China;School of Electrical and Electronic Engineering ,North China Electric Power University, Beijing 102206 ,China;Information and Communication Company, State Grid Jibei Electric Power Company, Beijing 100053, China)
出处
《计算机技术与发展》
2018年第5期197-200,共4页
Computer Technology and Development
基金
国家自然科学基金(51507063)
关键词
流量预测
分层可重构感知
神经网络
片上网络
并行处理
traffic prediction
hierarchical reconfigurable perceptron
neural network
nelwork on a chip
parallel processing
