摘要
SpacWire(SpW)高速数据总线协议规定了其通信链路10 Mbps的启动速率,这使得SpW数据接口必须要能提供10 MHz的时钟(DDR数据传输的情况下为5 MHz)。在某些特殊的应用场景下,比如要求更低的待机功耗,PCB板没有该指定时钟输入或者系统时钟分频无法提供该指定时钟等,直接降低启动速率会造成链路初始化连接失败[3]。文中提出SpW高速数据总线在低于标准启动速率下建立链路的方法,对协议分析获得相应的数值,并进行仿真验证。仿真测试表明,该方法在低于标准的链路启动速率下,链路可以成功建立,具有较高的应用价值。
SpaceWire（SpW）high speed data bus protocol defines its start-upsignaling rate of its communication link as 10 Mbps,which makes the SpW interface must be able to provide 10 MHz clock（for double data rate is 5 MHz）. In some special application scenarios,it may be impossible to provide the specified clock for the SpW interface. In this paper,the method of setting up the link under the standard start-up rate of SpW is proposed. The corresponding theoretical parametersis obtained by theoretical analysis,and tested by simulation.The board test shows that the link can be successfully established under standard initiate signaling rate. The method is of high value.
作者
柳萌
安军社
周昌义
LIU Meng;AN Jun-she;ZHOU Chang-yi(University of Chinese Academy of Science,Beijing 100190,China;National Space ScienceCenter,Key Laboratory of Integrated Avionics and Information Tecnology for Complex Aerospace Systems,Beijing 100190,China)
出处
《电子设计工程》
2018年第18期140-144,共5页
Electronic Design Engineering
