摘要
针对宽带小步进频综的低杂散、低相位噪声要求,本文提出了一种简易可行的频率合成方案。频率合成方案的基本框架由DDS激励锁相环构成,DDS通过可变参考时钟实现宽带低杂散输出,锁相环则基于高鉴相频率降低环内杂散与相位噪声恶化。试验结果符合设计要求,在L波段范围内频率步进为1 Hz,杂散抑制不小于70 dB,相位噪声小于-107.1 dBc/Hz@1 kHz。采用该方案设计的频综具有宽带小步进、低相噪、低杂散等特点,且电路方案简单易于实现小型化设计,具有较好的应用前景。
Aiming at the low spurious and low phase noise requirements of frequency synthesizer with wide band and small step,a simple and feasible frequency synthesis scheme is proposed. The basic framework of this scheme consists of DDS excitation phase-locked loop,the DDS achieve wideband output with low spurious by variable reference clock,and the phase-locked loop reduces spur and phase noise degradation in the loop based on high phase comparison frequency. The test results meet design requirements,which the frequency step is 1 Hz in L-band range,and spurious suppression is not less than 70 dB,and phase noise is less than-107.1 dBc/Hz@1 kHz. The frequency synthesizer designed by this scheme has the characteristics of wide band,small step,low phase noise and low spurs with simple circuit design and easy implementation of miniaturized design,which has a good application prospect.
作者
胡天涛
杜勇
田静
HU Tian⁃tao;DU Yong;TIAN Jing(Guizhou Aerospace Research Institute of Metrology and Testing Technology,Guiyang 550009,China)
出处
《电子设计工程》
2020年第1期118-122,共5页
Electronic Design Engineering
基金
贵州省科技计划项目(黔科合支撑[2016]2324)
关键词
频综
宽带
低杂散
小步进
小型化
frequency synthesizer
wide band
low spurious
small step
miniaturization
