摘要
针对共源二倍频器匹配电路版图面积较大和传统共基二倍频器变频增益低的问题,本文提出一种二次谐波短路的共基二倍频器电路.共基结构和共源结构相比输出电容较小使得匹配电路尺寸较小,同时在输入端引入二次谐波短路电路,有效提升了共基二倍频器的变频增益.该二倍频器由Push-push二倍频器电路和驱动放大器构成,其中前者用来产生二倍频信号,后者用来对二倍频信号进行放大输出以便驱动二倍频器的后一级电路.基于对晶体管偏置与二次谐波输出功率关系的研究,将晶体管偏置在AB类提升了输出功率和变频增益.输入端共模点接地减小了输入匹配的相位误差,提升了基波抑制和三次谐波抑制.驱动放大器采用共发射极放大器结构,输出匹配部分采用并联电阻变压器结构用于提升匹配带宽.测试结果表明,在输入功率为2 dBm的条件下,3 dB带宽绝对频率范围是13.8~23.2 GHz(相对带宽50.8%),基波抑制带内优于32 dB,功率附加效率达到19%(输出功率5.2 dBm,直流功耗16 mW).二倍频器芯片(核心区域,不含测试焊盘)面积仅为0.245 mm^(2).
To overcome the problems of the larger layout area of the common source and the low conversion gain of the traditional common-base doubler,this paper proposes a common base doubler circuit with a second harmonic short-circuit.Compared with the common source structure,the output capacitance of the common-base structure is smaller,thus the matching circuit is smaller.Moreover,the second harmonic short circuit is introduced at the input end,which effectively improves the frequency conversion gain of the common-base doubler.The frequency doubler is composed of a Push-push double frequency doubler circuit and a driving amplifier.The former is used to generate a second harmonic signal,and the latter is used to amplify the second harmonic signal to drive the second-stage circuit of the frequency doubler.The influence of the transistor bias on the output power of the second harmonic was evaluated,and the transistor bias was placed in Class AB to improve the output power and conversion gain.The input common mode point grounding reduces the phase error of the input matching,and improves the fundamental wave suppression and third harmonic suppression.The driver amplifier(DA)adopts a common emitter amplifier structure,and the output-matching part of the DA adopts a parallel resistance transformer structure to increase the matching bandwidth.The test results showed that the 3 dB bandwidth absolute frequency ranged from 13.8 to 23.2 GHz(50.8% relative bandwidth),and a fundamental rejection of better than 32 dB at an input power of 2 dBm and a power-added efficiency(PAE)of 19%(output power of 5.2 dBm and power consumption of 16 m W)was also achieved.The chip size was(core area without test pad)0.245 mm^(2).
作者
傅海鹏
郑玉学
陆敏
Fu Haipeng;Zheng Yuxue;Lu Min(School of Microelectronics,Tianjin University,Tianjin 300072,China;ZTE Corporation,Shenzhen 518057,China;State Key Laboratory of Mobile Network and Mobile Network and Mobile Multimedia Technology,Shenzhen 518057,China)
出处
《天津大学学报（自然科学与工程技术版）》
EI
CAS
CSCD
北大核心
2022年第5期504-511,共8页
Journal of Tianjin University：Science and Technology
基金
国家自然科学基金资助项目(62074110)
国家重点研发计划基金资助项目(2018YFB2202500)。
