期刊文献+

The circuit design and optimization of quantum multiplier and divider 被引量:1

原文传递
导出
摘要 A fault-tolerant circuit is required for robust quantum computing in the presence of noise.Clifford+T circuits are widely used in fault-tolerant implementations.As a result,reducing T-depth,T-count,and circuit width has emerged as important optimization goals.A measure-and-fixup approach yields the best T-count for arithmetic operations,but it requires quantum measurements.This paper proposes approximate Toffoli,TR,Peres,and Fredkin gates with optimized T-depth and T-count.Following that,we implement basic arithmetic operations such as quantum modular adder and subtractor using approximate gates that do not require quantum measurements.Then,taking into account the circuit width,T-depth,and T-count,we design and optimize the circuits of two multipliers and a divider.According to the comparative analysis,the proposed multiplier and divider circuits have lower circuit width,T-depth,and T-count than the current works that do not use the measure-and-fixup approach.Significantly,the proposed second multiplier produces approximately 77%T-depth,60%T-count,and 25%width reductions when compared to the existing multipliers without quantum measurements.
出处 《Science China(Physics,Mechanics & Astronomy)》 SCIE EI CAS CSCD 2022年第6期11-25,共15页 中国科学:物理学、力学、天文学(英文版)
基金 This work was supported by the National Natural Science Foundation of China(Grant Nos.61762012,61763014,and 62062035) the Science and Technology Project of Guangxi(Grant No.2020GXNSFDA238023).
  • 相关文献

同被引文献8

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部