摘要
基于0.7μm InP HBT工艺,设计了连续时间超高速宽带Σ-Δ模数转换器,其时钟采样率为10 GS/s.该模数转换器系统包括两级环路滤波器,一个2 bit ADC和一个2 bit DAC.为了方便测试,电路中还增加了2 bit DAC和输出缓冲电路.设计完成后的Σ-ΔADC电路版图整体尺寸为1.58 mm×1.82 mm.电路后仿真结果表明:当时钟采样率为10 GS/s时,该ADC电路在输入信号频率为307 MHz时的带内无杂散动态范围为52.4 dB,信噪比为42.6 dB;在5 V电源电压下,电路的总功耗约为1.3 W.
A continuous time ultra-high speed broadbandΣ-Δanalog-to-digital converter(ADC)with a clock sampling rate of 10 GS/s was presented based on 0.7μm InP HBT process.The ADC system included a two-stage loop filter,a 2-bit analog to digital converter(ADC)and a 2-bit digital to analog converter(DAC).In order to facilitate the test,a 2 bit DAC and an output buffer were added to the circuit.Circuit layout size ofΣ-ΔADC was 1.58 mm×1.82 mm.The post simulation results show that when the sampling rate is 10 GS/s,for input signal frequency of 307 MHz,the ADC circuit has a spurious free dynamic range(SFDR)of 52.4dB and a signal-to-noise ratio(SNR)of 42.6dB.The ADC consumes 1.3 W under a supply voltage of 5 V.
作者
张翼
刘坤
韩春林
王洋
张有涛
李晓鹏
杨磊
郭宇锋
ZHANG Yi;LIU Kun;HAN Chunlin;WANG Yang;ZHANG Youtao;LI Xiaopeng;YANG Lei;GUO Yufeng(College of Integrated Circuit Science and Engineering,Nanjing University of Posts and Telecommunications,Nanjing 210023,China;National and Local Joint Engineering Laboratory of RF Integration and Micro-assembly Technology,Nanjing 210023,China;Science and Technology on Monolithic Integrated Circuits and Modules Laboratory,Nanjing 210016,China;State Key Lab.of Millimeter Waves,Southeast University,Nanjing 210096,China;Nanjing Vocational University of Industry Technology,Nanjing 210023,China;Nanjing GuoBo Electronics Co.,Ltd.,Nanjing 210016,China)
出处
《中北大学学报（自然科学版）》
CAS
2022年第6期554-559,共6页
Journal of North University of China(Natural Science Edition)
基金
微波毫米波单片集成和模块电路重点实验室基金资助项目(614280304012101)
东南大学毫米波国家重点实验室开放课题(K202220)
射频集成与微组装技术国家地方联合工程实验室开放课题(KFJJ20210206)。
