摘要
采用敏捷硬件开发语言Chisel,对数字系统设计中经常使用的异步先进先出(FIFO)进行设计,使用Chisel语言特性提高了设计效率和质量。使用ChiselTest框架对所设计的异步FIFO进行基本功能仿真验证,使用通用验证方法学(UVM)进行更加完备的功能仿真验证,再使用QuartusⅡ软件进行逻辑综合。对比使用Chisel语言与使用传统硬件描述语言(HDL)设计的异步FIFO综合结果,结果表明,使用传统HDL语言设计的异步FIFO消耗了50个组合逻辑单元,而使用Chisel语言设计的异步FIFO,综合后仅消耗了39个组合逻辑单元。
Using Chisel,an agile hardware development language,the asynchronous first in first out(FIFO)commonly used in digital system design is designed,and language features of Chisel are used to improve the efficiency and quality of the design.The basic functional simulation verification of the designed asynchronous FIFO is carried out using the ChiselTest framework,the more complete functional simulation verification is carried out using the universal verification methodology(UVM),and the logic synthesis is carried out using the QuartusⅡsoftware.The synthesis results of asynchronous FIFOs designed with Chisel language and traditional hardware description language(HDL)are compared.The results show that the asynchronous FIFO designed with traditional HDL language consumes 50 combinational logic units,while the asynchronous FIFO designed with Chisel language consumes only 39 combinational logic units after synthesis.
作者
蒋文成
黄嵩人
JIANG Wencheng;HUANG Songren(School of Physics and Optoelectronics,Xiangtan University,Xiangtan 411105,China)
出处
《电子与封装》
2024年第9期66-70,共5页
Electronics & Packaging
