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一种高PSRR超低噪声CL-LDO设计 被引量:1

A High PSRR Ultra-Low Noise CL-LDO Design
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摘要 提出了一种高电源抑制比(PSRR)超低噪声无片外电容低压差线性稳压器(CL-LDO)。采用自偏置折叠共源共栅结构的自适应误差放大器降低系统噪声;利用过温保护电阻和电流增强电阻的基准电压源结构,使电压基准源在高工作电压下具有较高PSRR;同时在电流源正温度系数支路引入一对温度系数相反的电阻,简化电流源零温度系数调节过程。该CL-LDO基于CSMC 0.18μm BCD工艺进行电路验证,该电路在输出电容为1 pF,电源电压为4.9 V~5.2 V,负载电流为200μA至90 mA条件下,可稳定提供3.3 V电压输出,电源抑制比为-44 dB@10 kHz,等效输入噪声仅为17nV/√Hz@100kHz。电源电压5 V时具有12.1μV/mA的负载调整率和4.8 mV/V的线性调整率。阶跃负载电流上升/下降时间为1μs的情况下,该CL-LDO恢复时间小于2.2μs。 A high power supply rejection ratio(PSRR)ultra-low noise,capacitor-less low dropout linear regulator(CL-LDO)is proposed.An adaptive error amplifier with a self-biasing folded cascode structure is used to reduce system noise.High PSRR at high apply voltages is provided by using the reference voltage source structure with an over-temperature protection resistor and a current enhancement resistor.The zero-temperature coefficient regulation of the current source is simplified through a pair of resistors with opposite temperature coefficients in the positive temperature coefficient branch of the current source.The CL-LDO is based on the CSMC 0.18μm BCD process and is proven to provide a stable 3.3 V output under the condition of the output capacitance being 1 pF,a supply voltage being 4.9 V-5.2 V and a load current being 200μA to 90 mA,with a supply rejection ratio of-44 dB@10 kHz and an equivalent input noise of only 17 nV/√Hz@100kHz.The load regulation rate is 12.1μV/mA and the linear regulation of 4.8 mV/V at 5 V supply voltage.The CL-LDO recovery time is less than 2.2μs when the step load current rise/fall time is 1μs.
作者 姚佳 武华 冯秀平 陈翰民 杨煌虹 曾伟 曹先国 YAO Jia;WU Hua;FENG Xiuping;CHEN Hanmin;YANG Huanghong;ZENG Wei;CAO Xianguo(College of Physics and Electronic Information,Gannan Normal University,Ganzhou Jiangxi 341000,China;Sichuan Xinsheng Xinguo Technology Co.,Ltd.,Chengdu Sichuan 610000,China)
出处 《电子器件》 CAS 2024年第5期1173-1180,共8页 Chinese Journal of Electron Devices
基金 国家自然科学基金项目(61650404) 江西省教育厅科技项目(GJJ201411)。
关键词 无片外电容低压差线性稳压器 超低噪声 电源抑制比 负载调整率 线性调整率 capacitor-less low dropout linear regulator ultra-low noise power supply rejection ratio load regulation ratio linear regula-tion ratio
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  • 1孙毛毛,冯全源.LDO线性稳压器中高性能误差放大器的设计[J].微电子学,2006,36(1):108-110. 被引量:10
  • 2郭鹏,沈相国.LDO的三种频率补偿方案实现[J].电子器件,2006,29(3):706-709. 被引量:8
  • 3马超,刘永根,薛卫东,张波.一种高温段指数曲率补偿电压基准源[J].微电子学,2007,37(3):436-439. 被引量:9
  • 4拉扎维B.模拟CMOS集成电路设计[M].西安:西安交通大学出版社,2003
  • 5Allen P E,Holberg D R(著).CMOS模拟集成电路设计[M].冯军,李智群(译).北京:电子工业出版社,2005.
  • 6GIANLUCA G. A detailed analysis of power-supply noise attenuation in bandgap voltage references [ J]. IEEE Trans Circ and Syst, 2003, 50(2): 185-197.
  • 7THAM K, NAGARAJ K, A low supply voltage high PSRR voltage reference in CMOS process [J]. IEEE Sol Sta Circ, 1995, 30(5): 586-590.
  • 8Tesch B J,Pratt P M,Bacrania K,et al. A 14-b 125 MSPS Digital-to-Analog Converter and Bandgap Voltage Reference in 0.5 μm CMOS[C]//Proc. of the IEEE 1999 ISCAA'99. Orlando,FL,USA:[s.n.], 1999:452-455.
  • 9Banba H,Siga H,Umezawa A,et al. A CMOS Bandgap Reference with Sub-l-V Operation[J]. IEEE Journal of solid-state Circuits, 1999,34(5):670-674.
  • 10Paul R Gray,Paul J Hurst,Stephen H Lewis,et al. Analysis and design of analog integrated circuits[M]. New York:John Wiley & Sons, 2001:299-327.

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